`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:04:03 10/13/2013 
// Design Name: 
// Module Name:    TopNexys3 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TopNexys3(
	input clk,
	inout [7:0] DB, //these are all wires for Depp protocol
	input EppWRITE,
	input EppASTB,
	input EppDSTB,
	output EppWAIT,
	output [7:0] seg, //7 seg 
	output [3:0] an,
	output [7:0] Led,
	input [7:0] sw,
	input [4:0] btn,
	inout PS2KeyboardData,
	inout PS2KeyboardClk,
	inout PS2MouseData,
	inout PS2MouseClk,
	output [2:0] vgaRed,
	output [2:0] vgaGreen,
	output [2:1] vgaBlue,
	output Hsync,
	output Vsync,
	inout [7:0] JA,
	inout [7:0] JB,
	inout [7:0] JC,
	inout [7:0] JD	
    );
	 
	 reg clk_50Reg;
	 always @(posedge clk) clk_50Reg <= ~clk_50Reg;
	 
	 BoardConfiguration boardConfigurationInstance(clk, clk_50Reg, EppASTB, EppDSTB, EppWRITE, EppWAIT, DB, Led, sw, btn, seg[6:0], seg[7], an, PS2KeyboardClk, PS2KeyboardData, PS2MouseClk, PS2MouseData, vgaRed, vgaGreen, vgaBlue, Hsync, Vsync, JA, JB, JC, JD);
	 
	 


endmodule
